library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;

entity mux_4to1 is
    Port ( X0 : in  STD_LOGIC_VECTOR(7 downto 0); --Входы
           X1 : in  STD_LOGIC_VECTOR(7 downto 0);
           X2 : in  STD_LOGIC_VECTOR(7 downto 0);
           X3 : in  STD_LOGIC_VECTOR(7 downto 0);
           C : in  STD_LOGIC_VECTOR(1 downto 0); --Управление
           D : out  STD_LOGIC_VECTOR(7 downto 0)); --Выход
end mux_4to1;

architecture BEH of mux_4to1 is
begin
    process(C, X0, X1, X2, X3)
    begin
        case C is
            when "00" => D <= X0;
            when "01" => D <= X1;
            when "10" => D <= X2;
            when "11" => D <= X3;
            when others => D <= (others => '0');
        end case;
    end process;
end BEH;